4 Sequential Logic Circuits, State Machines

4.2 The Base Flip-Flop

The most elementary class of Sequential Logic Circuits is formed by the so-called "Flip-Flops" (Abbreviation "FF"). Contrary to the combinational circuits the devices are characterized by the existence of an internal storage. Because of this memorizing ability the knowledge of the current input states is not sufficient in this case to describe the complete function. The current state of the internal storage must also be known (which essentially refers to the activity "history" of the device).

The most simple Flip-Flop circuit shall be characterized by the following three functions:

• the FF output can be switched to "1"
  ("Set" function of the FF),
• the FF output can be switched to "0"
  ("Reset" function of the FF),
• After applying Set or Reset to the FF the output shall remain stable ("Store" function, storing the information)

These three FF functions can be shown in a simple timing diagram:

Figure 4.4: Simple Timing Diagram of a Flip-Flop.

Flip-Flops can be considered fast electronic switches, that can for instance be used to keep the inputs of a combinational circuit stable, until all signal changes have passed through:

Figure 4.5: Flip-Flop Application.

The "switches" FF₁ and FF₂ have to fulfil certain requirements as a prerequisite for a failure-free behaviour of the above circuit:

• The interconnection "Data - Q" must be interrupted as long as glitches (i.e. disturbing pulses) exist;
• The connection may only be established when the data are stabilized;
• At FF₁ the feedback signal must be delayed by at least the maximum signal propagation time in the combinational circuit CC₁.
  

Observation:

In the typical Flip-Flop application shown here, the identifier X and Y refer to so-called bus systems, i.e. a collection of equivalent signal lines to one connection bundle. This "bundle" can for instance combine 8 lines and therefore carry 1 byte of signals. The flip-flop FF2 is available in a corresponding number (1 flip-flop per signal).

This configuration using Flip-Flops (FFs) in a parallel setup is called a "Register".
Obviously the Flip-Flop FF₂ is part of a register. Functioning like an input switch for the combinational circuit CC₂ it receives the output signals from CC₁ and keeps them stable. Consequently the signals can propagate through CC₂ while in CC₁ a new "signal vector" is already evaluated. The individual results can even be produced at different times.

Because of the register (FF₂) the input values of CC₂ are not affected by any signal changes.

When the FF register remains in its storage position this will prevent the propagation of noisy signals produced in CC₁ to CC₂.

Obviously the same considerations are valid for the inputs of CC₁ and therefore also for the feedback signal. This feedback can be interrupted by Flip-Flop FF₁ whereby the timing behaviour will be changed. CC₁ in connection with FF₁ can be considered a new sequential logic circuit SC1.

In case that at the input of CC₁ new values should only be accepted when all previously triggered signal waves have faded away, FF₁ must block all feedback signals up to the longest propagation time in CC₁ (delay time t_D).

From this application the fundamental requirements that a basic flip-flop has to fulfil can directly be derived. The following timing diagram summarizes the required temporal and logical behaviour of the flip-flop:

Figure 4.6: Timing and Logic Behaviour of a basic Flip-Flop.

An approximate solution would be possible with a dual-edge control, in which a programmable delay time t_d should exist between the transfer of information with the flip-flop and the information output:

Figure 4.7: Dual-Edge Control.

4.2.1 Design of a Latch Flip-Flop

As a simple example a hypothetical Latch-FF will be developed first. This flip-flop shall be characterized by two distinguishable states:

• "Pass" (Unlatch):
  The signal at the data input will be transferred to the output.
• "Lock and Hold" (Latch):
  The value of the input signal will be "frozen" immediately before this state is entered and remains available at the output until the end of this state.

For this flip-flop the circuit symbol below (hypothetical as well) could serve for a full description:

A tabular functional description (function table, truth table) can also be developed:

In the K-Map stable and non-stable states can directly be distinguished:

Figure 4.9: K-Map of the Latch Flip-Flop.

When Q⁺ indicates the state of the FF after the change of the input parameters, then obviously the following "store" and "hold" conditions will be valid:

.

(4.1)

The stable states have been circled (in red) in the K-Map.

This description becomes even clearer using the state diagram (state transition diagram) introduced before (see above):

Figure 4.10: State transition diagram of the Latch Flip-Flop.

From the state transition diagram can be seen that this circuit has only two stable states, into which in can be transferred applying the corresponding input signals. Because of this property this circuit is also know as a "Bistable Flip-Flop".

A typical gate implementation of this flip-flop shows clearly the storage function implemented using a feedback structure:

Figure 4.11: Gate Implementation of a Latch Flip-Flop (hypothetical).

Function describing the Latch Flip-Flop:

(4.2)