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Circuit Symbols according to ANSI/IEEE Std 91a-1991 (IEEE Standard Graphic Symbols for Logic Functions)
The following table summarizes the most important circuit symbols as defined by the IEC/ANSI/IEEE standards.
OR Element
The output stands at its 1-state if and only if one or more of the inputs stand at their 1-states. | |
AND Element
The output stands at its 1-state if and only if all inputs stand at their 1-states. | |
Logic Threshold Element
The output stands at its 1-state if and only if the number of inputs that stand at their 1-states is equal to or greater than the number in the qualifying symbol, represented here by m. | |
m and only m Element
The output stands at its 1-state if and only if the number of inputs that stand at their 1-state is equal to the number in the qualifying symbol, represented here by m. | |
Majority Element
The output stands at its 1-state if and only if the majority of the inputs stand at their 1-states. | |
Logic Identity Element
The output stands at its 1-state if and only if all inputs stand at the same state. |
Addition-mod-2-Element
(ODD element, ODD-parity element, addition modulo 2 element) The output stands at its 1-state if and only if the number of inputs that stand at their 1-state is odd (1, 3, 5, etc.). | |
EVEN Element, EVEN-parity Element
The output stands at its 1-state if and only if the number of inputs that stand at their 1-states is even (0, 2, 4, etc.). | |
Buffer without specially amplified output
The output stands at its 1-state if and only if the input stands at its 1-state. | |
Negator, Inverter (in the case of device representation using a
single logic convention)
The output stands at its external 0-state if and only if the input stands at its external 1-state. | |
Inverter (in the case of device representation using direct polarity indication) The output stands at its L-level if and only if the input stands at its H-level. |
The Inverter symbol shows that attributes can be added to inputs, outputs and other connections, in order to show a logic negation or polarity, respectively:
Logic negation, shown at an input. The external 0-state produces the internal 1-state. | |
Logic negation, shown at an output. The internal 1-state produces the external 0-state. | |
Logic polarity, polarity indicator shown at an input. The L-level on the input produces the internal 1-state. | |
Logic polarity, polarity indicator shown at an output. The internal 1-state produces the L-level on the output. | |
Active-low input in the case of signal flow from right to left. | |
Active-low output in the case of signal flow from right to left. |
Table 1.11: Negation, polarity, and dynamic input symbols.
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